High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking dice vertically and interconnecting the dice using through-silicon (or through-substrate) vias (TSVs). Benefits of the 3D memory devices include shorter interconnects which reduce circuit delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM).
For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance random access memory (DRAM) interface and vertically stacked DRAM. FIG. 1 is a wiring diagram of a High Bandwidth Memory (HBM) 1 and a processor 2. For example, the processor 2 may be a graphical processor unit. The HBM 1 may include terminals coupled by balls 3 (e.g., microbumps) to an interposer 5. The processor 2 may include terminals coupled by balls 4 (e.g., microbumps) to the interposer 5 and further to the corresponding terminals of the HBM 1 through the interposer 5. The interposer may be stacked on a packaging substrate (not shown) by balls 6. For example, the interposer 5 may be made of silicon.
FIG. 2A is a schematic diagram of an HBM stack including an interface (I/F) die 22 and a plurality of core dies 23. For example, the number of the plurality of core dies 23 in the HBM stack 21 may be four. FIG. 2B is a schematic diagram of a portion of the HBM stack 21. The I/F die 22 and the plurality of core dies 23 may be coupled by a plurality of conductive vias 27 (e.g., through silicon (substrate) via (TSV)). The I/F die 22 may be on the balls 3. For example, a combination of the conductive vias 27 and the balls 3 may function as interconnects. FIG. 2C is a schematic diagram of the HBM stack 21 including the I/F die 22 and the plurality of core dies 23. The HBM stack 21 may have two 128-bit channels per core die for a total of eight input/output channels and a width of 1024 bits in total. For example, each core die of the plurality of the core dies 23 may include two channels. In this example, the core dies 23a, 23b, 23c and 23d include channels A and C, channels B and D, channels E and G, and channels F and H, respectively. For example, a clock frequency, a command sequence, and data can be independently provided for each channel.
FIG. 4A is a wiring diagram of the HBM stack 21 including the I/F die 22 and the plurality of core dies 23. The I/F die 22 of the HBM 21 provides interfaces 28a, 28b, 28e and 28f which provide signals on four input/output channels among the eight input/output channels, which function independently of each other. Memory arrays of the channel A, channel B, channel E and channel F of the core dies 23a, 23b, 23c and 23d may be coupled to the I/F die 22 via native input/output lines (IOs) 27a, 27b, 27e and 27f, respectively. For example, the native IOs 27a to 27f may be implemented as conductive vias. For example, the conductive vias may have a spiral structure. Each core die 23 may include a command circuit for each channel. For example, the core dies 23a to 23d may include command circuits 26a to 26d for channel A, channel B, channel E and channel F, respectively. Thus, clock signals, command signals and data signals for each channel may be transmitted independently and a plurality of data buses and their respective channels can operate individually.
FIG. 3A is a schematic diagram of an HBM stack 31 including an interface (I/F) die 32 and a plurality of core dies 33. For example, the number of the plurality of core dies 33 in the HBM stack 31 may be eight. FIG. 3B is a schematic diagram of the HBM stack 31 including the I/F die 32 and the plurality of core dies 33. The HBM stack 31 may have two 128-bit channels per core die for a total of eight input/output channels and a width of 1024 bits in total. For example, each core die of the plurality of the core dies 33 may include two channels. In this example, a stack group 34a having a stack identifier (SID) “0” includes the core dies 33a, 33b, 33c and 33d including channels A and C, channels B and D, channels E and C, and channels F and H, respectively. A stack group 34b having a stack ID (SID) “1” includes the core dies 33e, 33f, 33g and 33h including channels A and C, channels B and D, channels E and G, and channels F and H, respectively. Thus, a destination die among a plurality of core dies in each channel (e.g., core dies 33a and 33e of channel A) addressed in a command may be identified by the SID.
FIG. 4B is a wiring diagram of the HBM stack 31 including the I/F die 32 and the plurality of core dies 33. The I/F die 32 of the HBM 31 provides interfaces 38a, 38b, 38e and 38f which provide signals on four input/output channels among the eight input/output channels of two stack groups. Memory arrays of channels A, B, E and F of the stack group 34a and memory arrays of channels A, B, E and F of the stack group 34b may be coupled to the same native input/output lines (IOs) 37a, 37b, 37e and 37f, respectively. For example, memory arrays of channel A of the core die 33a in the stack group 34a and memory arrays of channel A of the core die 33e in the stack group 34b may be coupled to the native IO 37a. Each core die 33 may include a command circuit for each channel. For example, the core dies 33a to 33d in the stack group 34a may include command circuits 36a to 36d for channel A, channel B, channel E and channel F, respectively. The core dies 33e to 33h in the stack group 34b may include command circuits 36e to 36h for channel A, channel B, channel E and channel F, respectively. Each command circuit 36 may detect the SID in a command, check whether the SID in the command matches with an SID of the stack group of the core die 33 including the command circuit 36, and decode the command if the SID matches and memory access actions responsive to the command may be performed. For example, when the interface 38a transmits a command on the input/output line 37a, the command circuit 36a receives the command and check whether the SID in the command is “0”. The command circuit 36a processes the command if the SID is “0” and ignores the command if the SID is “1”. The command circuit 36e also receives the command and check whether the SID in the command is “1”. The command circuit 36e processes the command if the SID is “1” and ignores the command if the SID is “0”. Thus, clock signals, command signals and data signals for each channel on each die may be transmitted independently.
FIG. 5 is a command truth table of various combinations of a clock cycle, a clock enable signal, row command/address signals to be provided to the HBM 1. For example, a command circuit for each channel on each die may receive a plurality of row command/address signals R[5:0], the CKE signal and the clock signals. In the command truth table, “H” represents a logic high signal, “L” represents a logic low signal, RA[15:0] represents a row address, BA[3:0] represents a bank address, “PAR” represents parity information, and “V” represents a corresponding bit that can be either “H” or “L” which is a defined logic high or low level. Functions of row commands may include Row No Operation (RNOP), Activate (ACT), Precharge (PRE), Precharge All (PREA), Single Bank Refresh (REFSB); Refresh (REF), Power Down Entry (PDE), Self Refresh Entry (SRE) and Power Down & Self Refresh Exit (PDX/SRX). The SID may be provided at a rising edge of the ACT command, at a falling edge of R[1] of the PRE command or the REFSB command.
FIG. 6 is a command truth table of various combinations of a clock cycle, a clock enable signal, column command/address signals to be provided to the HBM 1. Description of components corresponding to components included in and previously described with reference to FIG. 5 will not be repeated. For example, a command circuit for each channel on each die may receive a plurality of column command/address signals C[7:0], the CKE signal and the clock signals. In the command truth table, CA[6:0] represents a column address and OP[6:0] represents operands to be written. Functions of column commands may include Column No Operation (CNOP), Read (RD), Read w/AP (RDA); Write (WR), Write wi AP (WRA), and Mode Register Set (MRS). As shown in FIG. 6, the SID may be provided at a falling edge of R[1] of the RD command, the RDA command, the WR command, or the WRA command. The RDA command or WDA command with auto-precharge may be used when an auto-precharge occurs to a bank associated with the command. As shown in FIGS. 5 and 6, the CKE signal is active (e.g., “H”) while a command is being provided. As earlier mentioned, each command circuit may detect the SID in a command, and check whether the SID in the command matches with an SID of the stack group of the core die of the command circuit. The SID may be included in the falling edge of the clock cycle of the commands (e.g., PRE, REFSB, RD, RDA, WR and WRA). For example, as shown in FIG. 4B, when the interface 38a transmits a command on the input/output channel 37a, the command circuit 36a receives the command and checks whether the SID in the command is “0” or “1”.
FIG. 7 is a timing diagram of clock signals and command signals to be provided to a portion of dies in the HBM stack 31. For example, the portion of dies may be an I/F die 32 die, Core 1 die 33a, and Core 5 die 33e in FIG. 4B. For example, the timing diagram of FIG. 7 includes a clock signal CK_t and column command signals C[7:0] received at the I/F die 32, a clock signal CK_t_0 and column command signals C_0[7:0] received at the Core 1 die 33a which processes a command for channel A in a stack group with SID=“0”, and a clock signal CK_t_1 and column command signals C_1[7:0] received at the Core 5 die 33e which processes a command for channel A in a stack group with SID=“1”. The I/F die 32 receives a command from a first clock cycle of the clock signal CK_t at time T0. The I/F die 32 may capture an SID included in the command at a falling edge of the first clock cycle of the CK_t signal at time T1. The Core 1 die 33a may capture the SID at a falling edge of a first clock cycle of the CK_t_0 signal at time T2. The core 5 die 33e receives the SID at a falling edge of a first clock cycle of the CK_t_1 signal at a time T3. There may be a propagation delay from the I/F die 32 to the Core 1 die 33a represented by “T2-T1.” There may be a propagation delay from the Core 1 die 33a to the Core 5 die 33e represented by “T3-T2.” The command circuits 36a and 36e Core 1 die 33a and the Core 5 die 33e wait for the SID until the falling edge of the first clock cycle and determine whether the SID corresponds to the core die of the command circuit. When a command is issued to the Core 1 die 33a, the command related signals may be transmitted to the Core 5 die 33e, because the Core 1 die 33a may capture the SID at time T2 after the first clock cycle of the commands for the Core 5 die 33e may be transmitted. The command circuit 36a of the Core 1 die 33a may not be able to determine whether the command is for the Core 1 die 33a or for the Core 5 die 33e until capturing the SID. The command circuit 36e of the Core 5 die 33e may not be able to determine whether the command is for the Core 5 die 33e until capturing the SID. If the propagation delay may be about half a clock cycle, the SID may be captured by the command circuit 36e about a propagation delay of a clock cycle. Thus, command signals unnecessary for the Core 5 die 33e may be transmitted until the SID is captured at time T3.